This invention relates to the digital communication arts and, more particularly, to a means for reducing the length of a transmission bit stream by combining synchronization bits with data bits and obtaining frame synchronization at the receiver by using a multiphase sequential decoder.
Digitally encoded communication systems are well known in the art. In such systems, a data bit stream containing digitally encoded information is transmitted over a noisy transmission medium. If the raw information data were transmitted without any error correction processing, there would exist a substantial probability that portions of the message might be irretrievably lost due to interference from the noisy medium. Therefore, this data is normally processed to produce a transmission bit stream, which, after decoding at the receiver, provides a means to correct or minimize transmission medium induced errors. Two examples of error correction processing schemes are the block and convolutional type codes.
Proper decoding of the transmission bit stream requires that the decoder be able to recognize and synchronize the received bit stream signal. This process is called frame synchronization. To assure proper decoding synchronization, the prior art has utilized a predetermined set of synchronization (sync) bits preceding the data bits. For example, N sync bits of a specific pattern may be transmitted, such as the well known Barker sequence, which optimizes the ability of the decoder to recognize and synchronize with the transmission bit stream. This is done by correlating the received bit stream with a reference pattern.
For short messages of less than about 200 channel bits, an improvement may be obtained by combining of the data bits with the sync bits by a modulo 2 adder, i.e. an exclusive OR function. The resulting transmission bit stream then has a total of less than the number of information bits plus the number of sync bits, thereby substantially minimizing the number of bits required to send the message. The decoder and the receiver then regenerate the data bit stream by another modulo 2 addition of the transmission bit stream with the sync bits stored within the decoder at the receiver to yield the original data bits. This technique is disclosed in U.S. Pat. No. 4,158,748 to John En issued June 19, 1979 and entitled "Apparatus for Digital Data Synchronization", which is assigned to the assignee of the present invention. The method disclosed in this patent utilizes a threshold detector which performs one complete correlation operation for each assumed start position, or phase, of the input data. That is, one complete frame synchronization attempt is needed per channel bit received.
A shortcoming of the aforementioned synchronization scheme is that a relatively significant amount of time is required to perform a decode operation for each received channel bit. In addition, a substantial number of information bits must be predefined as an identification sequence which can be correlated with the same predefined sequence stored at the decoder to detect frame synchronization. The requirement for a predefined information bit sequence necessarily reduces the effective number of information bits which may be specified in each code word to substantially less than N.
In some systems such as those which utilize master-slave or hand-shaking operations, or operate in a slotted contention mode, the frame synchronization phase will be known to within P bit positions. In such a case, it is very desirable to find a method of decoding such that the time required to perform a frame synchronization operation does not linearly increase with P. However, it should be noted that in instances where the phase is totally unknown, it may be assumed that the frame synchronization is within P bits. Then if the message is not detected during those P bit positions, after an erasure the decoder can look at the next P bit positions until the frame synchronization is found.